The present invention relates to a mobile telephone using a liquid crystal display (LCD) for the display portion.
FIG. 3 is a block diagram showing the structure of an address data bus for a mobile telephone using a LCD in its display portion. In FIG. 3, when information specifying an address is output from the CPU 1 for performing processing such as internal computations and controls, same information is transmitted to all of a data writable/readable internal RAM 2, an internal ROM 3 in which executable programs are stored, a DAC (D/A converter) 4 for converting signals from digital to analogue, a timer 5 for timing and counting an elapsed time, a RF controller 6 for controlling radio, a LCD controller 15 for controlling a liquid crystal display, a non-volatile SRAM 8, and a FLASH/ROM 9. In other words, it is constructed in such a manner that by controlling any one of blocks connected to the CPU 1 via an address data bus 10 shown above, the same information is transmitted to all other blocks connected to the CPU 1 via the address data bus 10.
However, in the mobile telephone of recent years, the level of downsizing, weight reduction, and slimming down is ever increasing, and therefore, the structure is changing in such a manner that the LCD located on the upper part of the terminal is getting closer to the antenna. As shown in FIG. 4, in the case where the structure is such that the LCD 13 mounted to the mobile telephone 12 is locate in the vicinity of the antenna 14, there is a recognized disadvantage in that the receiving sensitivity of the antenna 14 is deteriorated due to the noise generated from the address data bus connected to the LCD 13. It is because the distance between the antenna 14 and the LCD 13 is getting shorter with the advance of downsizing, and consequently the noise from the address data bus connected to the LCD 13 is apt to be transmitted to the antenna 14.
It is conceivable to reduce the noise from the address data bus by lowering the voltage on the bus line frequently, however, since the CPU 1 is also connected to a block of which the access timing is fast, it is impossible to lower the voltage of the bus line frequently.